1. Field of the Invention
The present invention relates to a packet switching apparatus which handles a number of input lines and a number of output lines. More particularly, the present invention relates to a packet switching technique to be used for switching a large number of packets at high speed. The present invention, for example, is applicable to ATM (Asynchronous Transfer Mode) switching which is designed for switching fixed-length packets.
2. Description of the Related Art
FIG. 6 shows a block diagram of a conventional ATM switch designed for switching fixed-length packets. (The conventional ATM switch is disclosed in a technical report entitled “B-519: A Large-scale ATM Switch Architecture for Multimedia Traffic”, General Assembly 1996 of Communication Society, The Institute of Electronics, Information and Communication Engineers)
Reference numerals 1-1 to 1-n denote input lines. Reference numerals 2-1 to 2-n denote transfer lines. A reference numeral 3 denotes a packet switching unit. A reference numeral 4 denotes an MUX (multiplexer) which is included in the packet switching unit 3. Reference numerals 5-1 to 5-n denote buffers. Reference numerals 6-1 to 6-n denote line corresponding units. Reference numerals 8-1 to 8-n denote buffers.
The packet switching unit 3 is configured so as to sort data packets received through the input lines 1-1 to 1-n into the transfer lines 2-1 to 2-n. The packet switching unit 3 is provided with the buffer stores 5-1 to 5-n which correspond, respectively, to the transfer lines 2-1 to 2-n. Each of the buffer stores 5-1 to 5-n is configured so as to store the data packets.
The line corresponding units 6-1 to 6-n are provided, respectively, with the buffer stores 8-1 to 8-n. Each of the buffer stores 8-1 to 8-n is configured so as to store the data packets received through a corresponding one of the transfer lines 2-1 to 2-n and outputs the data packets through a corresponding one of the output lines 7-1 to 7-n.
The operation of the conventional ATM switch is now discussed. The packet switching unit 3 sorts data packets (ATM cells) received through the input lines 1-1 to 1-n into the line corresponding units 6-1 to 6-n corresponding respectively to the output lines 7-1 to 7-n.
Specifically, the MUX 4 multiplexes the data packets received through the input lines 1-1 to 1-n. In addition to that, the MUX 4 outputs multiplexed data to the buffer stores 5-1 to 5-n, respectively.
Each of the buffer stores 5-1 to 5-n stores data packets to be outputted to a corresponding one of the line corresponding units 6-1 to 6-n alone. Each of stored data packets is read out at a transfer speed k×V(k>1) which is faster than a line speed V used by the output lines 7-1 to 7-n. Readout data packets are transferred through the corresponding one of the transfer lines 2-1 to 2-n.
The throughput is increased more by thus reading out the data packets at the transfer speed k×V(k>1) faster than the line speed V than by reading out the data packets at the line speed V. Increased throughput thus obtained allows a reduction in the size of the individual buffer stores 5-1 to 5-n.
The line corresponding units 6-1 to 6-n store the data packets received through the corresponding ones of the transfer lines 2-1 to 2-n in their own buffer stores 8-1 to 8-n. Stored data packets are then read out at the line speed V of the respective output lines 7-1 to 7-n and outputted through the output lines 7-1 to 7-n.
As discussed earlier, the buffer stores to be used for switching data packets are thus provided in a decentralized manner in the packet switching unit 3 and the line corresponding units 6-1 to 6-n. This can reduce the size of a buffer store 5 (which is a generic term of the buffer stores 5-1 to 5-n included in the packet switching unit 3) which requires a high speed performance at a speed of (N number of output lines×line speed V).
In particular, in the case of ATM switching for switching fixed-length packets, it may be effective to minimize the size of the circuit which is to perform at high speed.
However, there is a problem of the conventional packet switching apparatus thus configured requiring the high-speed performance circuits as many as the number of output lines.